Silicon photonic circuits generally route optical signals in planar waveguides, and it is difficult to provide a path for light to enter/exit the circuits vertically. Routing light in or out of the wafer surface can be valuable for several reasons, such as coupling into a normal-incidence photodetector on the wafer surface, for wafer-level optical test/characterization, or other potential applications.
Of particular interest is the integration of planar silicon waveguides with Ge-based photodetectors. This is being addressed in several ways, all of which have various challenges. Planar photodetectors, in which the Ge is grown on top of the Si waveguide are quite large, because the optical coupling is inefficient and a long distance is needed for sufficient coupling of light to occur from the Si to the Ge.
To avoid this difficulty, trench sidewall photodetectors have been proposed, where the waveguide is terminated by a vertical facet. In this case, a facet with sufficient smoothness is difficult to form, and the epitaxial growth of the Ge-based photodetector can be very challenging.
Coupling light to and from planar silicon photonic devices, particularly in a low-cost, high volume manufacturing (HVM) compatible way, represents a significant challenge, and a major hurdle to commercialization. Currently, manual techniques are required to prepare facets on the edges of silicon photonics chips at the die level to couple light to and from the devices.
Currently, input facets are prepared manually by dicing and polishing at the die level. FIG. 1 shows a cross-sectional side view of a photonic waveguide including a Si handle wafer 100, a buried oxide layer 102, and an Si device layer 104. A re-entrant mirror (REM) 106 may be formed in the device layer 104 as similarly described in co-pending application Ser. No. 12/567,601, herein incorporated by reference. A device, such as a photodetector 108 may be over the re-entrant mirror 106. The coupling of light into and out of the silicon waveguide is done through facets 110 at the die edge that are prepared by dicing and mechanical polishing at die-level. This is a tedious manual process, which is not scalable to HVM. Grating couplers may also be used, but these have high loss for larger (>1 um) waveguide based devices and require a high-profile package, because they are inherently non-planar.